Greetings, dear readers!
Did you know that the name Tianjic in Chinese carries a double meaning? On one hand, it signifies a "heavenly mechanism" or "sublime plan," and on the other, it symbolizes the union of different worlds. This reflects the essence of Tianjic: the integration of two artificial intelligence paradigms (ANN and SNN) into a single chip. In the first part of the article, we explored the history of Tianjic’s creation and its key technical solutions. Now it’s time to discover how the "heavenly" architecture of Tianjic performs in practice and the challenges it faces on the road to establishing the hardware foundations of AGI.
System Programming
The programming of Tianjic is a multi-layered development chain specifically adapted for a hybrid architecture capable of executing both traditional artificial neural network (ANN) computations and spiking signal (SNN) processing. Below is a detailed breakdown of each stage of this chain.
1. Overall Architecture of the Software Toolchain
The Tianjic software ecosystem includes a specialized compiler that automatically transforms neural network models created in popular frameworks (such as TensorFlow or PyTorch) into a configuration suitable for distributing computational loads across FCore. The compiler analyzes the network architecture and determines which layers or blocks should be implemented in ANN mode and which in SNN mode. Moreover, the compiler performs weight quantization, converting the parameters trained with floating-point operations into an 8-bit representation with minimal loss of precision, and optimizes resource allocation by automatically assigning computational cores to execute various parts of the model—a critical factor for achieving high parallelism and energy efficiency.
2. Frontend: Model Development
A developer creates a neural network model using familiar tools and frameworks: in ANN mode, standard deep learning libraries are used for classical operations such as convolutional, fully connected, and recurrent layers, while in SNN mode specialized frameworks or converted ANN models may be used to simulate temporal dynamics or event-based representations. After the model is described in a high-level language, its parameters—including structure, weights, and activation functions—are passed to the Tianjic compiler, which adapts them to the hardware constraints and architectural specifics of the hybrid chip.
3. The Process of Compiling and Mapping the Model onto Hardware Resources
After the model is input, the compiler analyzes it and distributes the computations among 156 specialized FCore cores, taking into account the need to operate in both modes. Each core is programmed according to its assigned task: it can function as a classic artificial neuron or as a spiking neuron (with leakage dynamics and threshold-based activation), which allows the hardware to be flexibly adapted to different layers of the network. In the final stage, inter-core communication is configured, defining data routing through an asynchronous 2D network that supports the transmission of both continuous values and events in the AER (Address-Event Representation) format.
4. Debugging and Simulation
For effective development and debugging, specialized tools are provided. A chip simulator allows emulation of Tianjic’s operation before the model is loaded onto the physical chip, ensuring the correctness of partitioning and configuration. Visualization tools enable tracking of task distribution among cores and analyzing the asynchronous data exchange—a particularly important aspect for hybrid models with differing computational characteristics. Performance profiling tools assess the energy efficiency and inference execution time, which is crucial for optimizing the system's real-time operation.
5. Approaches to Training and Weight Transfer
It is important to note that Tianjic is designed exclusively for inference, while neural network training is carried out on external computing platforms. Initially, models are trained on GPUs or other devices that support floating-point operations, allowing for high accuracy. Subsequently, a conversion is performed: weights are quantized, and the model is adapted to the hardware characteristics of Tianjic, such as 8-bit operations and the use of local SRAM. For SNNs, two approaches are possible: an indirect method, in which an equivalent ANN model is first trained and then converted to a spiking form, and a direct method, which involves the use of specialized gradient-based learning algorithms adapted for discrete spiking signals—a process that requires additional optimization techniques.
6. Features of Hybrid Programming
The hybrid architecture of Tianjic imposes specific demands on the software. The ability to combine layers with continuous and spiking computations in a single model requires the compiler to account for differences in data representation and neuron operation logic. The software environment must adjust the parameters of each FCore based on the task being executed, ensuring the system’s versatility, albeit complicating the development process. Moreover, integration with existing ecosystems demands support for popular frameworks, which simplifies porting models to Tianjic but requires additional abstraction layers to manage the hardware specifics of the hybrid architecture.
The Tianjic programming chain demonstrates the integration of traditional deep learning methods with innovative solutions for working with spiking neural networks. A specialized compiler, automatic model partitioning, efficient data routing, and tools for simulation and debugging create a comprehensive environment for developing hybrid neural networks. This system enables researchers and engineers to develop solutions that combine the advantages of both ANN and SNN, opening up new opportunities for creating energy-efficient and high-performance intelligent systems.
Practical Demonstration of Tianjic: The Autonomous Bicycle as a Test Platform for AGI
The culmination of the development was a demonstration project—a self-driving bicycle controlled by a single Tianjic chip. In the experiment described in Nature, researchers equipped the bicycle with a camera, gyroscope, ultrasonic sensors, and a motor, along with a computing module based on Tianjic. Multiple neural network models operated simultaneously on the chip: a convolutional neural network (CNN) processed the video feed from the camera for object and obstacle recognition; a spiking neural network managed balance and stabilization using gyroscope data; another module processed voice commands (words like “forward,” “stop,” etc.) using an impulse neural network; and a central unit—a kind of neural controller—made decisions based on all inputs. As a result, the bicycle was able to autonomously ride along the path: it maintained balance, avoided obstacles, recognized voice commands, and reacted to them (for example, turning on command).
This project clearly demonstrated that the hybrid chip is capable of uniting functions that require heterogeneous AI: computer vision, audio processing, and motion control—without external computational assistance. The entire intelligence of the "smart bicycle" was housed on a single Tianjic chip, consuming roughly 1W of power, whereas an equivalent system on conventional processors would require significantly more resources. This experiment became a milestone: it confirmed the viability of the Tianjic concept and its suitability for real-world applications (robotics, autonomous devices).
The demonstration with the autonomous bicycle is not merely a flashy experiment. It confirms the viability of the Tianjic hybrid architecture and its potential in creating universal intelligent systems. By implementing complex scenarios in the real world, Tianjic shows that hardware solutions can overcome the traditional separation between neuromorphic computations and classical machine learning. This is an important step towards creating platforms that can support a wide range of cognitive functions—from perception and recognition to decision-making and self-regulation—and brings us closer to the realization of systems with elements of artificial general intelligence (AGI).
Differences from SpiNNaker and TrueNorth
To highlight Tianjic’s features, let’s compare it with two well-known neuromorphic platforms: IBM TrueNorth (a hardware spiking chip) and SpiNNaker (a massively parallel neuromorphic computer for spiking networks). TrueNorth was the first full-scale neuromorphic chip (28 nm, 2014) with a fixed spiking architecture—1 million simple LIF neurons connected in a network and extremely low power consumption. However, it cannot perform deep network computations or learn, and its use is limited to tasks such as event and sensory signal recognition. In contrast, SpiNNaker is a cluster of many standard ARM cores simulating brain function in software—this provides flexibility (any neural network can be modeled, parameters can be changed on the fly), but the speed and energy efficiency of this approach are significantly lower than those of specialized hardware. Tianjic occupies an intermediate position: it combines the efficiency of a hardware solution (like TrueNorth) with some versatility (like SpiNNaker). Unlike TrueNorth, Tianjic supports not only spikes but also standard neural network computations (such as convolutional layers), and in some metrics even surpasses IBM’s creation—its internal memory and communication systems provide approximately 100× higher throughput, and its processing speed is an order of magnitude greater. Compared to SpiNNaker, Tianjic achieves significantly better energy efficiency on the same tasks due to its hardware implementation: for example, running an MLP or CNN on Tianjic is dozens of times faster and more economical than on an ARM cluster or GPU. Thus, the main distinction of Tianjic is its ability to handle a hybrid workload on a single chip: running both deep learning algorithms and neuromorphic computations simultaneously. This makes it a unique experimental tool for AGI research, although the lack of on-chip learning and limited scalability impose certain constraints.
Limitations and Challenges
Despite the significant advantages of Tianjic’s hybrid architecture, there are certain limitations and challenges that must be considered when developing and applying this technology. Let’s highlight the main issues:
1. Hardware Architecture Limitations
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Lack of On-Chip Learning. Tianjic is primarily designed as an accelerator for inference and currently supports only pre-trained models. The absence of on-chip learning mechanisms means that updating weights and adapting the model in real time is not possible. This limits its application in tasks that require dynamic adaptation, such as systems with continuous feedback or online learning.
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Limited Computational Precision. Using 8-bit arithmetic for representing weights and activations ensures high energy efficiency; however, it may become a bottleneck for tasks with high precision requirements. Although tests indicate that the loss of precision is minimal, in some applications (e.g., those with a wide dynamic range of signals) this might limit the model’s capabilities.
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Scalability and Integration. A single Tianjic chip emulates approximately 40,000 neurons and 10 million synapses. For implementing large neural networks, multiple chips must be combined into arrays. This raises issues of inter-chip communication: ensuring synchronization, managing latency, and maintaining energy efficiency when scaling up remain significant technical challenges.
2. Software and Algorithmic Challenges
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Complexity of Hybrid Programming. The hybrid nature of Tianjic requires the compiler and development tools to support two paradigms (ANN and SNN) simultaneously. This complicates the process of model partitioning, distribution of computational tasks among FCore, and optimization of inter-core routing. The presence of two types of computations places additional demands on optimization algorithms, which may lead to inefficient use of hardware resources in complex models.
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Debugging and Profiling. The asynchronous nature of data exchange between cores, coupled with the mixture of continuous and spiking computations, creates challenges in debugging and profiling the system’s performance. Traditional performance analysis tools may not account for the specifics of hybrid computations, necessitating the development of specialized diagnostic and optimization tools for Tianjic.
3. Ecosystem and Developer Support Limitations
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Immaturity of the Software. Currently, the Tianjic software toolchain is available on a limited basis, which hinders widespread adoption of the technology among researchers and developers. The absence of an open Software Development Kit (SDK) and restricted access to documentation may slow down the development of an ecosystem around the chip and reduce the number of experiments involving hybrid neural networks.
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Compatibility with Existing Frameworks. Although the model can be described using popular frameworks (TensorFlow, PyTorch), the process of converting and optimizing it for the Tianjic architecture requires additional effort. Integrating with existing tools can be challenging due to the need to consider the specifics of handling asynchronous events and SNN mode, which necessitates additional layers of abstraction.
4. Thermal and Energy Constraints
While a single Tianjic chip demonstrates extremely low power consumption (~1 W), when combining a large number of chips to solve complex tasks, the issue of thermal management may become significant. Effective distribution of thermal loads and ensuring stable operation under high loads require additional engineering solutions at the system integration level.
Tianjic is not just a new chip, but a comprehensive architectural concept that integrates the best practices from neurobiology and deep learning. It demonstrates how disparate approaches can be effectively combined to create a universal and scalable platform capable of supporting both specialized tasks and complex multitasking systems. We see enormous potential in the hybrid approach and are confident that further research in this area will lead to the development of more advanced AGI systems.
We invite you to join the discussion on this topic: What are your thoughts on the prospects of hybrid computing platforms? What other challenges and opportunities do you see on the path to realizing AGI? Share your thoughts and ask questions in the comments!
Thank you for being with us! Regards, the MemriLab Team!
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